1. Field of the Invention
The present invention relates to a balanced modulator for use in a microwave frequency band.
2. Description of the Related Art
Conventional balanced modulators are disclosed in Japanese patent laid-open publications Nos. 83166/81, 138108/83, and 91341/91.
FIG. 1A of the accompanying drawings shows in cross section the balanced modulator disclosed in Japanese patent laid-open publication No. 83166/81.
As shown in FIG. 1A, the balanced modulator includes a strip conductor pattern 20 of gold or the like disposed on a ceramic substrate 22. The strip conductor pattern 20 includes conductors 20a, 20b serving as input terminals for a carrier, and conductors 20c, 20d serving as output terminals for a modulated signal. The balanced modulator also has diodes D.sub.1, D.sub.3, D.sub.4, D.sub.2 connected directly to the conductors 20a, 20b, 20c, 20d, respectively. The diode D1 has a cathode connected to the conductor 20c by a gold wire 24, and the diode D.sub.3 has a cathode connected to the conductor 20d by a gold wire 26. The diode D.sub.2 has a cathode connected to the conductor 20a by a gold wire 28, a gold wire 30 extending through a through hole defined in the ceramic substrate 22, and a gold wire 32. The diode D.sub.4 has a cathode connected by a gold wire 34 to a joint land 36 that is connected to the conductor 20b by a gold wire 38 extending through a through hole defined in the ceramic substrate 22, and a gold wire 40.
A stub 42 having a length of .lambda. (.lambda. is the wavelength at a frequency used) is inserted between and connected to the conductors 20c, 20d, and a stub 44 having a variable length 1 is connected between the conductor 20a and the joint land 36. A bias current whose polarity depends on the polarity of a pulse signal is supplied through the stubs 42, 44 to the balanced modulator.
FIG. 1B of the accompanying drawings shows in plan the balanced modulator disclosed in Japanese patent laid-open publication No. 138108/83.
As shown in FIG. 1B, the balanced modulator has a pair of diodes D.sub.1, D.sub.2, a pair of capacitors C.sub.1, C.sub.2 connected in series to the diodes D.sub.1, D.sub.2, respectively, a conductor pattern 51 connected to electrodes of the capacitors C.sub.1, C.sub.2, and a pair of bias supply terminals B.sub.1, B.sub.2 connected to the junctions between the diodes D.sub.1, D.sub.2 and the capacitors C.sub.1, C.sub.2. The balanced modulator also includes an outer conductor pattern 52 and a branch slot line 53.
FIG. 1C of the accompanying drawings shows in plan the balanced modulator disclosed in Japanese patent laid-open publication No. 91341/91.
As shown in FIG. 1C, the balanced modulator comprises a pair of diodes 61, a pair of impedance conversion lines 64 connected to anodes or cathodes of the diodes 61, a 3.lambda./2 line 65 connected to ends of the impedance conversion lines 64, an output combining line 71 connected to opposite ends of the impedance conversion lines 64, a pair of low-frequency signal voltage applying lines 66, a local frequency signal input line 67, a modulated signal output line 68, a pair of first adjustment lines 69, and a pair of second adjustment lines 70.
For adjusting the isolation of the balanced modulators, the stub 44 of the balanced modulator shown in Japanese patent laid-open publication No. 83166/81 and the first and second adjustment lines or stubs 69, 70 of the balanced modulator shown in Japanese patent laid-open publication No. 91341/91 are varied in length to cancel out a reactive signal component produced by the diodes for thereby moving a point O representative of the isolation along a virtual axis as shown in FIGS. 2A and 2B of the accompanying drawings. To move the point O along a real axis, it is necessary to apply an offset current (offset voltage) as disclosed in Japanese patent laid-open publication No. 138108/83, as shown in FIG. 2C of the accompanying drawings.
Applying an offset current (offset voltage), however, results in the problem of an increased amplitude error.